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Modeling, Synthesis, and Rapid Prototyping with the VERILOG (TM) HDL

Modeling, Synthesis, and Rapid Prototyping with the VERILOG (TM) HDLAuthor: Michael D. Ciletti
Publisher: Prentice Hall
Category: Book

List Price: $156.00
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Rating: 3.0 out of 5 stars 11 reviews
Sales Rank: 1,161,054

Media: Hardcover
Edition: Bk&CD-Rom
Pages: 724
Number Of Items: 1
Shipping Weight (lbs): 2.9
Dimensions (in): 9.6 x 7.3 x 1.4

ISBN: 0139773983
Dewey Decimal Number: 621.392
EAN: 9780139773983
ASIN: 0139773983

Publication Date: March 18, 1999
Availability: Usually ships in 24 hours
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Product Description
Designed for advanced undergraduate and graduate computer science, computer engineering and electrical engineering courses in digital design and hardware description languages, this textbook presents an integrated treatment of the Verilog hardware description language (HDL) and its use in VLSI, circuit modeling/design, synthesis, and rapid prototyping. This product is a selection from the Xilinx Design Series.

Customer Reviews:
Showing reviews 1-5 of 11
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1 out of 5 stars Awful, Impractical, Unreadable   November 20, 2009
kj (Canada)
Do not buy this book.

Of course, it is out of date. That is not the author's fault, as it was published before Verilog 2001. Everything else *is* his fault, however.

This book does not present material in an order that is useful for learning the language. It is not skimmable. It is not easy to just "look something up." Useful information, if there is any, is buried deeply in meaningless exposition. The emphasis placed on the material does not correspond with any design methodology I am familiar with.

This book says a log about nothing. Read Sections 8.1 - 8.5, for instance, including such material as "Benefits of Synthesis". Design is about synthesis. Synthesis is the whole *point*.

This book uses blocking assignments in sequential logic. It uses nonblocking assignments in combinational logic. This is not just bad style. It is dangerous advice (especially in the former case)

Examples in this book are so simple as to be trivial. Examples should be edifying, not obvious.

Having been through this book far too many times, now, I am *still* left with no clear idea who it was written for. It is clearly not a practical book for someone looking to pick up Verilog quickly. It certainly has *nothing* to do with rapid prototyping, despite the title. It does not clarify anything that couldn't be more easily gleaned from the Verilog Standard itself.

In short, I'm sorry I ever bought this book. It has wasted more of my time than it has ever saved. Instructors: AVOID using this book in your courses, please. Designers, pick somthing else.


4 out of 5 stars Good Book   November 1, 2007
Ketan Kulkarni (USA)
This book is not the a quick start verilog book. It is a comprehensive verilog bible kind of a book and hence a good reference. There are explanations for everything from syntax, usage, to pitfalls and subtleties. If you are going to buy only one book and intend to learn verilog seriously I would recommend this book. If you are just tinkering with verilog however and want to experiment only for a while, you should consider one of the "learn verilog in 24 hours" or quick start verilog books.


3 out of 5 stars Text for grad engineering class   September 20, 2005
UMKC student
0 out of 1 found this review helpful

First printing has some different problem numbers from other printings. Check the printing number against class requirements.


4 out of 5 stars Recommended.   November 30, 2003
Stephen Henry (Scotland, UK)
1 out of 1 found this review helpful

I am using this book for an introductory Verilog class at my University and I must say I am truely confused by some of the reviews here. Although this book takes the reader through the most basic elements of the Verilog language, to its more complex and esoteric uses, most people here complain that the it fails to provide the advanced, cutting-edge examples they feel it should have. What? Do you really expect to learn how to build a Pentium IV from a book teaching the basics of Verilog? Get real!

This book teaches the basics, it teaches you how to use the Verilog language by providing examples that, although dated, illustrate timeless approaches that are used in every Verilog design large or small. If you can't find how to complement a variable, then its your fault, not the book; I can assure you its there. Furthermore, if you think that pointing out a few mistakes in the book, (and have obviously learnt the correct way of doing it from it), makes it rubbish, then I'm afraid there won't be any books that will fully satisfy your needs.

This is one of the best books I've encountered on the Verilog langauge. Although I wouldn't say it's as good as, say, Ashendens VHDL, it is _not_ as bad as some of the reviews here make out. Recommended!


2 out of 5 stars Writing is far from refined   February 26, 2003
1 out of 4 found this review helpful

The writing is fragmented and incomplete statements are often seen, for example:

1. in section 4.6.4, it is written
"If A and B are vectors, A&&B returns true if both words are
positive integers." then no words there to specify "otherwise" part. If you assume otherwise A&&B returns false, you are wrong,
since A&&B returns true when both are negative integers too.

2. In 7.5.1, it says "There are two forms for delay control,...
The first form is ...", but the second form is never explained or mentioned there.

3. You often see
always @ ( a or b ) in examples with "or" in boldface,
but I could not find where "or" is defined. Even though I
understand its meaning, I wish to tell the differece from
using "|" , "||"

4. ... plus many typos

These cause a lot confusion in reading

Showing reviews 1-5 of 11
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